AN1879 application note how to use the m41st87w tamper detect and ram clear introduction the m41st87w is a supervisory family circuit that provides the industry with the latest in onchip security solutions. the tamper detection and ram clear circuit can be used in any system to protect sensitive data from tampering. this chip can be used to secure a wide range of applications from credit card machines and point - of - sale (pos) terminals to electric d ata meters. the m41st87w features the ability to detect and timestamp any tampering of the system, and corrupt the device memory when the event occurs. this prevents the intruder from accessing data stored in memory by clearing the device memory and/or ext ernal ram when the tampering event occurs. october 2013 docid010159 rev 5 1 / 8 www.st.com
contents AN1879 contents 1 description ....................................................................................... 3 1.1 how it works ...................................................................................... 3 1.2 clearing the external memory with the tamper registers ................... 3 1.3 clearing the external memory with an external charge pump ........... 3 1.4 ram clear data ................................................................................. 5 1.5 tamper timestamp ............................................................................ 5 2 conclusion ....................................................................................... 6 3 revision histo ry .............................................................................. 7 2 / 8 docid010159 rev 5
AN1879 description 1 description 1.1 how it works the m41st87w device provides two independent tamper input pins, tp1 in and tp2 in that can be used to monitor two separate signals. these two tamper input pins can be set to indicate that a tamper event has occurred by either 1) closing a switch (normally open) to ground or v out or 2) opening a switch that wa s previously closed (normally closed) to ground or v out . the closing and opening of the switch is configurable using bits that are set in the tamper registers. the m41st87w device includes 128 bytes of internal ram that the user has the option of clearing by setting the teb and clr bits in the tamper registers. 1.2 clearing the external memory with the tamper registers the m41st87w can also clear the external, battery - backed up sram of the device by setting the teb and clrext bits in the tamper registers. to clear/corrupt the external memory, v cc of the sram can be taken to ground. however, certain srams require a significant amount of time for the memory to be corrupte d if v cc is simply grounded. to corrupt the memory in a reasonable amount of time, one can take v cc of the sram to a negative voltage. by taking v cc to a negative voltage, the input protection diode turns on and goes into conduction mode so that it corrupt s the memory. 1.3 clearing the external memory with an external charge pump an external charge pump device should be used with the m41st87w to drive v cc of the sram to a negative voltage during the tamper condition. figure 1: "circuit connections" shows how to connect this circuit. when using the m41st87w with the charge pump device, the user must also provide two additional mosfets to isolate v out of the m41st87w from the output (out) of the charge pump during normal operation, and from v out of the m41st87w device during the tamper condition. during normal operation the tp clr signal will be forced low, disabling the charge pump. when d isabled, the output of most charge pumps will be forced to ground. in order to allow proper operation of the sram, mosfet(1) must be "off" to isolate v cc of the sram from the charge pump output. at this same time, the p - channel mosfet(2) will be "on" to pr ovide the supply voltage for the sram. during a tamper condition, the tp clr signal will be forced high, controlling the inhibit pin of the dc regulator. this will put the regulator in standby mode for t clr . the t clr is the tamper clear timing where the reg ulator will be switched off for 1, 4, 8, or 16 seconds, depending on the setting of the clrpw1 and clrpw0 bits in the register. the tp clr signal also enables the charge pump. when the charge pump is enabled, out generates a negative voltage on the v cc pin of the sram (for a programmable period of time), causing data corruption. the m41st87w must be isolated from the v cc of the sram to avoid data corruption of the m41st87w due to forward biasing of the parasitic diode of the m41st87w v out output. this is acc omplished by using the tp clr signal to turn the n - channel mosfet(1) "on," while turning the p - channel mosfet(2) "off." docid010159 rev 5 3 / 8
description AN1879 figure 1 : circuit connections 1. n - channel mosfet 2. p - channel mosfet 4 / 8 docid010159 rev 5 v cc pfo 1 ex sc l m41st87w wdi rstin1 rstin2 pfi 1 pfi 2 v ss v b a t f 32k irq/ou t sqw/f t rs t v ou t e con s d a cap+ cap? i n ve r ting cha r g e pump shdn ou t in tp1 in t p clr tp2 in push b utton reset pfo 2 l o w- p o w er sram v cc negati v e output (?1 x v in ) e t o rs t t o led displ a y (2) (1) t o nmi t o in t t o 32khz inhibit 5v regulator v cc v in c1 c2
AN1879 description 1.4 ram clear data depending on the process technology used to manufacture the external sram, clearing the memory may require varying durations of negative potential on the vcc pin. the m41st87w device allows the user to program the time needed for their particular application. the control bits clrpw0 and clrpw1, located in the day register, determine the duration of the tclr pulse width during a tamper event (see figure 2: "tamper output timing" ). thus, users can control the voltage and duration of the negative pulse enabling them to configure the circuit for many different lpsrams. figure 2 : tamper output timing note: see m41st87w datasheet for timing details. 1.5 tamper timestamp when the device is tampered with, and regardless of which tamper occurs first, a time stamp freezing the update of the clock registers will occur to let the user know when it was tampered with. the tamper bits (tb1 or tb2 in the flag register) will be set immediately. therefore, when tampering occurs, the user may elect to first read the time registers to det ermine exactly when the tamper event occurred, then read the flag register to see which tamper condition was triggered. the clock will update to the current time after resetting the teb bit in the tamper registers. the appropriate teb bit must always be re set to '0' in order to read the current time. the tamper detect function operates in v cc as well as in battery backup. docid010159 rev 5 5 / 8 t p clr v ou t rs t t amper event (tb bit set) high-z t t t e con irq/ou t high-z rec clr clrd
conclusion AN1879 2 conclusion with the increasing frequency of credit card fraud and identity theft, st is leading the way protecting this sensitive data with its new line of secure rtcs. this sensitive data is stored in internal or external memory of most devices like atm machines or pos terminals. the m41st87w solu tion can provide early detection when these devices have been tampered with and clear the ram before the intruder can access this data. 6 / 8 docid010159 rev 5
AN1879 revision history 3 revision history table 1: document revision history date revision changes 04- feb - 2004 1 first edition 12- apr - 2004 2 reformatted; updated vendor sram information (table 1) 03- jun - 2004 3 corrected drawing ( figure 1: "circuit connections" ) 16- jan - 2009 4 reformatted document; updated cover page, section 1.3: "clearing the external memory with an external charge pump" , figure 1: "circuit connections" , and ram clear data 16- oc t - 2013 5 removed table 1 (ram clear data with different vendors) and updated section 1.4: "ram clear data" docid010159 rev 5 7 / 8
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